# C2000 Solar MPPT tutorial Pt/3

In this third part of the C2000 Solar MPPT Tutorial, the software will be looked at in greater detail.  This will entail a look at the Perturb & Observe algorithm, ADC code and timing code to ensure everything operates in a controlled manner.

The software is based around a Perturb and Observe (P&O) algorithm, the P&O algorithm falls under the category of a hill climbing algorithm.  Hill climbing algorithms are named so due to the algorithm taking steps over sampled data to reach a desired value, in the case of the P&O this takes steps towards the MPP by increasing or decreasing the duty cycle.  There are other hill climbing algorithms such as dP/dV Feedback Control and Incremental Conductance, I intend to revisit these and write code at a later date, but for now will focus on the P&O.  Some further information on MPPT algorithms can also be found here.

## Perturb & Observe Algorithm

The P&O algorithm is a relatively simple algorithm, as such it has a few drawbacks:

• The algorithm can be confused and track in the wrong direction, this can occur under fast changing irradiance conditions, the severity of this confusion depends on the P&O setup i.e. step size and update frequency.
• The algorithm oscillates around the set point showing characteristics of an on/off controller.  More on this can be found on a previous tutorial I wrote regarding PID control, which can be found here.

The flowchart below shows the P&O algorithm used for this project

As can be seen from the flowchart the algorithm is fairly easy to follow, turning this into C code is also relatively easy, the final C code P&O algorithm can be seen below inside the function Adj_PWM().

So lets now run through the code briefly starting with line 3, this basically assigns the value in the counter compare A register to variable PWM_Temp.  PWM_Temp could simply be assigned to a temporary global variable, but I chose to get it straight from the register in this case.  Lines 5 to 24 form the main body of the algorithm, looking back at the flowchart the first two steps “Sample” and “Calculate” are carried out elsewhere in the ADC section of the code.  Lines 5 to 14 are illustrated by the right hand branch of the flowchart and lines 15 to 24 are illustrated by the left hand branch of the flowchart.

You have some simple if and else statements that determine which direction the algorithm takes, which is dependant on the sampled ADC data.  The result of these steps will either increase or decrease the PWM duty cycle, this increase or decrease determines the step size and in this case that value is 2.

The next block of code from lines 26 to 31 are used to prevent the duty cycle from reaching too large, and too small a value.  This was used during tuning, but also serves to provide some boundaries for the PWM, for example the duty cycle for the half bridge MOSFET drivers cannot exceed 99%, or the boost function will not operate correctly.

Lines 32 and 33 are used to update the duty cycle to the counter compare A registers for PWM1 and PWM2, both are the same duty cycle but PWM2 is 180o out of phase with PWM1.  Line 35 then assign the latest calculated solar panel voltage IP_Volt to the variable Old_IP_Volt and line 36 assign the latest calculated solar panel power New_PW_In to the variable Old_PW_In, both these variables are then used when the Adj_PWM() function is called again.

In order to help visualise the two PWM signals, the below image shows an oscilloscope trace with PWM1 in yellow and PWM2 in blue, both are set to 50% duty cycle and PWM2 is out of phase by 180o with PWM1.

The next piece of code to be looked at is the ADC, I am not going to show the set-up code for the ADC or the PWM that triggers the ADC SOC, but will just show the code relating to the sampling and calculation.  However I intend to write a tutorial on each peripheral inside the C2000 with code examples, when time allows.  The ADC sampling is triggered by the PWM on every first event, therefore the sampling rate is 15ksps.  The final ADC sampling code can be seen below inside the function Data_Update()

So starting with lines 3 to 6 these are the local variables used for the function, the two floats are used to store the ADC values and the two integers are used to determine how many samples in the for loop.  The float in line 4 is a float array with four arrays, now the same result could be achieved with four separate floats.  I have left it as a float array for now, but if four floats were used the code should be optimised, by using 64 samples the following division of 128 (lines 23 to 26) could be substituted with a right bit wise shift of 7.

Lines 23 to 26 divide the sum_of_ADC_samples_Array[n] by 128 and assign the value to ADC_An floats.  Lines 28 to 31 convert the new floats to real world voltages read on the GPIO. Lines 33 to 36 then use constant values calculated from the electronic component values in the circuitry, to convert the floats to actual voltages and currents sampled in the circuit.  Lines 38 to 40 simply convert the input voltage and current to an input power and the output voltage and current to an output power.

## Timing Code

The timing code is quite critical as it determines the update frequency of the MPPT, it must also ensure the code does not overrun and cause unpredictable behaviour.  The internal timer module was used, Timer 0 was set-up to trigger an interrupt every 100mS or 10Hz. The interrupt code is shown below.

When the interrupt is called an integer called SysTick is set to one, then the interrupt flag is cleared allowing the interrupt request to be executed and exited quickly.

Inside the main function there is a continuous while loop, the following code is run inside this loop.

Every time the interrupt sets the integer called SysTick to one, it allows the functions Data_Update() and Adj_PWM() to be executed, once these functions have completed SysTick is set to zero.  There are some additional lines of code on line 5 and line 10, these are used for testing and allowing the code execution time to be displayed on an oscilloscope.  The code on line 5 switches GPIO pin 19 high, then the code on line 10 switches GPIO pin 19 back to low, so a square wave pulse is produced and the pulse width gives an indication of the code execution time of the functions Data_Update() and Adj_PWM(). The following images show captures from an oscilloscope.

This first image shows the 15kHz PWM being displayed on channel 1, the individual wave pulses are not visible as the time base is set to display channel 2.  The blue trace shown on channel 2 can be seen to have a frequency of 10Hz, with a pulse width of 4.4mS, so the functions Data_Update() and Adj_PWM() take 4.4mS to execute.  Putting this into context there should be 128 ADC samples captured, taken from 64 triggers of the PWM signal, therefore 64*66.67uS (one 15kHz cycle) = 4.27mS.  A single ADC sample and conversion takes around 650nS, if we multiply that by the 8 samples, a conversion is being completed every 8*650nS = 5.2uS (it will be faster than this due to ADC pipelining effects).  It can be clearly seen that there is plenty of room for more oversampling if required, as the 5.2uS sample and conversion time easily fits inside the 66.67uS window of the PWM trigger.  There is also a small amount of code overhead being added artificially by toggling GPIO pin 19, which is not significant but something to be aware of.

The second image has a smaller time base setting (100uS) effectively zooming in, which allows the individual pulses from the 15kHz PWM to be visible.  So going back to the step size of 2 shown in the Adj_PWM() function, this can be put into context when the maximum duty cycle value as a variable, for 100% duty cycle equals 1000.  Therefore with a PWM update frequency of 10Hz and a maximum step size of 2, this equates to a maximum duty cycle change of 2% per second.

I captured some video which shows 3 variables being graphed in Code Composer Studio, these variables are PV Power, PV Volts and the Duty Cycle.  The video also demonstrates the MPPT in action under simulated fast changing cloud conditions, as well as some natural cloud.

There will be one final part to this series of tutorials this will cover some of the set-up and testing, and will also include a link to the full C code for the project.

I take great care when writing all the tutorials and articles, ensuring all the code is fully tested to avoid issues for my readers.  All this takes time and a great deal of work, so please support the site by using the Adfly links etc.  If you have found this useful or have any problems implementing, please feel free to leave a comment and I will do my best to help.

# C2000 Solar MPPT tutorial Pt/2

In this second part of the C2000 Solar MPPT Tutorial, the hardware and circuit design will be looked at in greater depth.  The schematic for the system is posted again below for reference, which can be enlarged by simply clicking on it.

## Buck Converter Design

The first step was to design the buck circuit, this is determined by the output parameters of the system and it’s load.  For the first prototype based around the panel purchased for testing, it was decided to aim for a 12V output, therefore a maximum current of 750mA (assuming 10% losses).

When calculating a buck circuit the frequency of operation, inductor size and output capacitor size are important, as they determine the current and voltage ripple size.  It is desirable to have as smaller current and voltage ripple as possible.  A large current ripple can cause additional losses in a system, as there maybe times when the peak current is greater than the load requirements.  A large voltage ripple is obviously not desirable, good quality regulated power supplies have very low voltage ripples.

A general rule is the higher the frequency the smaller the inductor and output capacitor size, and a smaller inductor and capacitor size generally lowers the system cost.  However higher PWM frequencies decrease the system efficiency due to switching losses in the mosfets, so a trade off has to be reached which meets the design constraints of the end system.

For this system a PWM frequency of 15kHz was chosen, based on this, the solar panel and other design parameters for the buck circuit calculations can be performed.  First we can determine the system duty cycle at MPP, note the duty cycle will change to track the MPP with differing irradiance.  A figure of 90% was used for the buck converter efficiency,a typically buck converter efficiency is 90% or greater.

Next an ideal current ripple can be determined, it is important to note that the below formulae used only determines a single phase current ripple.

ΔIL is the inductor ripple current, and in this case a 30% figure was used for the multiplier. Now that the current ripple is know the inductor size can be calculated with the following equation.

Using two 1.34mH inductors on each phase will ensure the inductor ripple current is effectively halved, knowing this an inductor ripple current of 90mA can be used to calculate the minimum output capacitor size.

Δvout is the desired ripple voltage.  The constant 8 is determined by the simplification of an equation, which can be found in various sources, one such source is an Application Note by On-Semiconductor AND9135/D.

There are two other factors for the inductor and capacitor that are important to consider: the inductor peak current and the capacitors Equivalent Series Resistance (ESR).  The inductor for this project will be hand wound using a toroidal core, which will be covered shortly.  The capacitors ESR can affect the reliability of the capacitor.  A capacitor will dissipate power as heat depending on it’s ESR, so a low ESR is desirable as excessive heating will shorten the life of a capacitor and be less efficient.  For this early prototype, cheap off the shelf capacitors were used as their reliability over time was not a concern at this stage.

The inductors were constructed using a T68-26A toroidal core, this core has a nominal inductance or Al value of 58nH.  The following equation was used to determine how many turns of wire the core would need.

A 0.3mm outside diameter enamelled cable was chosen, this has a maximum current rating of 1.4A.  Then a very useful website found here was used, this allows you to calculate the total length of cable required based on the toroidal core dimensions and cable diameter. Using a vice the cores were both wound and then measured using a LCR meter and measured at 1.3mH, an image below shows the hand winding process used.

## MOSFET Losses

For the prototype system Vishay IRFI640G MOSFETs were used, these are not the most efficient having a high RDSON value (180mΩ), but they were stocked at the time of writing.

The power losses from the High Side and Low Side MOSFETs are a combination of conduction and AC switching losses.  The conduction losses are a result of I²R losses inside the MOSFET when it is fully on, and the switching losses are the result of the MOSFET transitions from its on and off states.  Some example calculations will now be shown using data from the IRFI640G datasheet and various sources, on a synchronous MOSFET buck circuit efficiency.

The first equation is for the High Side MOSFET and is based on the Vmp of the solar panel at maximum output current running through each interleaved phase.

The next equation is for the Low Side MOSFET using the same current figure.

The results from these two equations can be combined to work out the overall efficiency, the losses will also be multiplied by a factor of 2 as this is for a two phase interleaved circuit.

Now if we increase the PWM frequency to 150kHz, the circuit losses will also be shown to increase.

The switching losses in this next example will be shown to increase with increasing current, the next example uses a 15kHz switching frequency but with 2A, increasing the overall power to 24W.

A MOSFET with a lower RDS(ON) will have lower conduction losses, but it will typically have a higher QG (Gate Charge) resulting in higher switching losses.  Therefore a careful balance between these characteristics should be found to maximise the circuits efficiency.  Taking into account the nominal parameters of the system, such as input voltage, output current, switching frequency and duty cycle, will allow the best efficiency to be achieved.  This will often involve using MOSFETs with different characteristics for the High and Low Side drivers.

## MOSFET Driver Circuit

The Half-Bridge (H-Bridge) driver is an IC designed specifically for driving MOSFETs. The IC takes the incoming PWM signal, and then drives two outputs for a High and a Low Side MOSFET.  This type of H-bridge is often used to to drive motors, but has other applications such as the following example.  The IC used is a IRS2003 half bridge driver made by International Rectifier, the image below shows an example circuit from the datasheet.

The IRS2003 allows 2 PWM signals to be connected to HIN and LINNot this gives the user the opportunity to fine tune the dead-band switching of the MOSFETs.  The capacitor wired between VB and VS along with the diode form a charge pump, this allows the drive voltage to the MOSFETs to be almost doubled.  HIN and LINNot in this case are wired together and supplied with the same PWM signal, the IRS2003 has internal timing to ensure the High Side MOSFET, and the Low Side MOSFET are never on at the same time.  The capacitor between VB and VS needs to be sized to ensure it can drive enough current to the gate of the chosen MOSFET, over coming the gate capacitance.

There are four ADC ports used on this project, two sampling voltage and two sampling current.  The hardware employed to sample the voltage signals will be covered first, followed by the current sampling circuit.  But first a brief introduction to the TMS320F28027 ADC.

The ADC measures voltage from 0V to 3.3V, with a 12bit resolution.  It is important to not exceed the input voltage of the microcontrollers GPIO pins, the TMS320F28027 has a maximum input voltage of 3.63V.  Using this information the step resolution for the ADC can be calculated.

The input on the ADC also has a small internal capacitance and resistance, this is used for Sample and Hold acquisition depending on the characteristics of the circuit being sampled. The internal ADC circuit taken from the TMS320x2802x datasheet is shown below.

To ensure the readings being sampled are as accurate as possible, the source resistance or RS shown in the above image ideally needs to be as small as possible.  This will be achieved by placing an opamp configured as a unity gain buffer in all the ADC sample circuits.  The unity gain buffer will ensure a high input impedance, therefore reducing loading effects on the sampled circuitry to a minimum, as well as offering a very low output impedance to the C2000 internal ADC circuit.  Rail to rail opamps were used and supplied with 3.3V, this ensured the voltage passed to the ADC would not exceed this, thus ensuring the system has ADC protection built in.

The voltage sampling circuits consist of a simple potential divider, the maximum voltage the solar panel can produce is 21.6V when open circuit.

The same resistor and opamp configuration is used for the input and output voltage measurement.  A more complex opamp circuit could have been used with offset, to fully exploit the range of the ADC, however this would provide more than enough accuracy for the prototype.

The current sampling circuit involved a slightly more complex approach.  The circuit would revolve around a Texas Instruments INA138 High Side Measurement current shunt monitor. The INA138 is basically a differential amplifier housed inside a small package, with a wide operating voltage.  The INA138 would be supplied with 12V, this then allows for a greater range to be measured around the 0V-3.3V range and was also the second supply voltage available for this circuit.  A typical configuration taken from the datasheet is shown in the image below.

There are differences in input and output current so two formulas would be needed to ensure the range was correct.  The shunt resistors comprised of two 1Ω (1%) resistors in parallel, so the combined value becomes 0.5Ω.  The parallel resistors were measured and the actual value was approximately 0.47Ω.  A quick calculation to check these could withstand the power loads was made.

This was not the best long term solution, but within tolerance for the 1% resistors in parallel.

The shunt resistor is connected directly across the internal differential amplifiers inputs. The calculations for the INA138 are fairly simple, the gain resistor soldered externally determines the overall gain of the device.  The datasheet for the INA138 states that the device has a gain of 1 with a 5kΩ resistor, gain of 2 with a 10kΩ, gain of 5 with a 25kΩ and so on and so forth. The input and output current gain resistors were calculated as follows.

These values would ensure the output from both the current feedback circuits falls in-line with the ADC input.

## Schematic Design and Layout

Certain aspects of the design were simulated in OrCad 16.6 first, to back-up the theory with simulation.  Then the design was taking over to EagleCad to enable faster prototyping.  Component symbols and foot prints where designed for all the non standard parts, ensuring these were all compatible with the LPKF milling machine used.  Once the schematic design was complete and the Electrical Rule Check (ERC) and Design Rule Check (DRC) were satisfactory, a schematic design was made for a two layer board.  The layout kept the PWM and digital switching side and analogue circuitry away from each other to avoid unnecessary noise.  The below image shows the final PCB prototype layout.

The next part of this tutorial will go more in-depth into the C2000 software and Perturb and Observe algorithm, also including a downloadable version of the C code.

I take great care when writing all the tutorials and articles, ensuring all the code is fully tested to avoid issues for my readers.  All this takes time and a great deal of work, so please support the site by using the Adfly links etc.  If you have found this useful or have any problems implementing, please feel free to leave a comment and I will do my best to help.